Novel Boolean logic manipulation : A symbolic computation and camouflaged graph construction
*Gete UmbreyCorresponding authorgete.umbrey@rgu.ac.inDepartment of MathematicsPasighatJawaharlal Nehru CollegeEast Siang, Arunachal Pradesh, 791102, IndiaView full profile → , Bhaba Kumar Sarmabks@iitg.ac.inDepartment of MathematicsIndian Institute of Technology GuwahatiGuwahati, Assam, 781039, IndiaView full profile → , Bhuban Chandra Deuribhuban.math@gmail.comDepartment of MathematicsPasighatJawaharlal Nehru College, PasighatEast Siang, Arunachal Pradesh, 791102, IndiaView full profile → , Alfonso Bustamanteathal.zigma@gmail.comDepartment of MathematicsSantiagoUniversity of ChileSantiago, 8320000, ChileView full profile → , Botem Moyongbotemmoyong.bm@gmail.comDepartment of MathematicsDara Natung Government CollegeItanagar, Arunachal Pradesh, 791111, IndiaView full profile →
* Corresponding author · click or hover a name for details
- Received:
- 01 Oct 2025
- Published Online:
- 02 Apr 2026
- Article type:
- Research Article
- Language:
- EN
- Article no.:
- JIOS-2220
- Pages:
- 1567–1589
Abstract
Keywords
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References
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