Design of an array multiplier in PFSCL style
*ShikhaCorresponding authorshikha.bvcoe@bharatividyapeeth.eduAffiliation 1Department of Electronics and Communication EngineeringBharati Vidyapeeth’s College of EngineeringPaschim Vihar, New Delhi, 110063, IndiaAffiliation 2Department of Electronics and Communication EngineeringDelhi Technological UniversityRohini, Delhi, 110042, IndiaView full profile → , Kirti Guptakirti.gupta@bharatividyapeeth.eduDepartment of Electronics and Communication EngineeringBharati Vidyapeeth’s College of EngineeringPaschim Vihar, New Delhi, 110063, IndiaView full profile → , Monica Guptamonica.gupta@bharatividyapeeth.eduDepartment of Electronics and Communication EngineeringBharati Vidyapeeth’s College of EngineeringPaschim Vihar, New Delhi, Department of Electronics and Communication Engineering Bharati Vidyapeeth’s College of Engineering, IndiaView full profile → , Preeti Nagrathpreeti.nagrath@bharatividyapeeth.eduDepartment of Computer Science and EngineeringBharati Vidyapeeth’s College of EngineeringPaschim Vihar, New Delhi, 110063, IndiaView full profile → , Bhawanand Jhabhawanand.jha@bharatividyapeeth.eduDepartment of Electronics and Communication EngineeringBharati Vidyapeeth’s College of EngineeringPaschim Vihar, New Delhi, 110063, IndiaView full profile → , Prakhar Sharmaprakhar.sharma@mediatek.comDepartment of Design4 MediaTek, U.S.A.View full profile → , Mauro Zannettimauro.zannetti@univaq.itDepartment of Industrial & Information Engineering and EconomicsUniversity of L’AquilaL’Aquila, I-67100, ItalyView full profile →
* Corresponding author · click or hover a name for details
- Received:
- 06 Aug 2024
- Published Online:
- 19 Feb 2025
- Article type:
- Research Article
- Language:
- EN
- Article no.:
- JIOS-1851
- Pages:
- 53–64
Abstract
Keywords
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References
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