Optimized vedic multiplier using low power 13T hybrid full adder
Mansi Jhambmansi.jhamb@ipu.ac.inUniversity School of Information, Communication & TechnologyGuru Gobind Singh Indraprastha UniversityNew Delhi, IndiaView full profile → , *Manoj KumarCorresponding authormanojkumar13578@gmail.comUniversity School of Information, Communication & TechnologyGuru Gobind Singh Indraprastha UniversityNew Delhi, India0000-0001-5113-0639View full profile →
* Corresponding author · click or hover a name for details
- Received:
- 02 Feb 2022
- Accepted:
- 02 Jul 2022
- Published Online:
- 28 Aug 2023
- Article type:
- Research Article
- Language:
- EN
- Article no.:
- JIOS-1222
- Pages:
- 675–687
Abstract
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References
[1] M. B. Murugesh, S. Nagaraj, J. Jayasree and G. V. K. Reddy, “Modified High Speed 32-bit Vedic Multiplier Design and Implementation,” 2020 International Conference on Electronics and Sustainable Communication Systems (ICESC), pp. 929-932 (2020), doi: 10.1109/ICESC48915.2020.9155882.
[2] Mukherjee, Biswarup, Biplab Roy, Arindam Biswas and Aniruddha Ghosal. “Design of a low power 4×4 multiplier based on five transistor (5-T) half adder, eight transistor (8-T) full adder & two transistor (2-T) AND gate.” Proceedings of the 2015 Third International Conference on Computer, Communication, Control and Information Technology (C3IT) : 1-5 (2015).
[3] Saradindu Panda, N. M. Kumar and C. K. Sarkar, “Transistor count optimization of conventional CMOS full adder & optimization of power and delay of new implementation of 18 transistor full adder by dual threshold node design with submicron channel length,” 2009 4th International Conference on Computers and Devices for Communication (CODEC), pp. 1-4 (2009).
[4] Amini Valashani, Majid & Ayat, Mehdi & Mirzakuchaki, Sattar. Design and analysis of a novel low-power and energy-efficient 18T hybrid full adder. Microelectronics Journal. 74. 49-59 (2018). 10.1016/j.mejo.2018.01.018.
[5] M. Zhang, J. Gu, C.H. Chang, A novel hybrid pass logic with static CMOS output drive full-adder cell, in: Int. Symp. Circuits Syst., ISCAS, Bangkok, Thailand, Very Large Scale Integr. VLSI Syst. 20 (7), 20–29. 3 (2002).
[6] S. Goel, A. Kumar, M. Bayoumi, Design of robust, Energy-Efficient full adders for Deep-Submicrometer design using Hybrid-CMOS logic style, IEEE Trans, Very Large Scale Integr. VLSI Syst. 14 (12), 1309–1321 (2006).
[7] M. Aguirre, M. Linares, CMOS full-adders for energy-efficient arithmetic applications, IEEE Trans. Very Large Scale Integration, J Circuit Syst. Compd., 26 (5), 240–260 (2017).
[8] Mansi Jhamb, Manoj Kumar, Vishal, Full Adder for Low Power Applications, International Journal of Innovative Technology and Exploring Engineering (IJITEE), ISSN: 2278-3075 (Online), Volume-9 Issue-4 (February 2020).
